1. Field of the Invention.
The present invention relates to pixel cells and, more particularly, to a pixel cell circuit having a nonsilicided photodiode region linked with a number of silicided MOS transistors by a photodiode access structure. Application of voltage to the photodiode access structure under a regular clocking schedule permits the photodiode to be selectively isolated and connected to the other elements of the pixel cell. Isolating the photodiode from the transistors in this manner shields the photodiode from leakage associated with silicided junctions, while permitting the photodiode to communicate voltage generated by incident light as an output of the pixel cell.
2. Description of the Related Art.
Recent imaging circuits use pixel cells to convert incident light energy into an electrical signal. In a typical pixel cell structure, a silicided photodiode is typically combined with a number of silicided MOS transistors which provide amplification, readout control, and reset control.
FIG. 1A shows a cross-sectional view of a conventional pixel cell. FIG. 1B shows a circuit diagram of the conventional pixel cell shown in FIG. 1A. As shown in FIG. 1A, a conventional pixel cell 110 includes a photodiode 111 and three MOS transistors: reset transistor 112, buffer transistor 113, and row select transistor 114. These conventional pixel cell circuit elements are arranged as described below:
Photodiode 111 is formed from the p/n junction between lightly doped P type substrate 115 and first heavily doped N region 116. First N+ region 116 has a silicided surface 117.
Reset transistor 112 has a source formed by photodiode 111 and a drain formed by second heavily doped N type region 118 connected to power supply node 119. Gate 120 of reset transistor 112 is connected to reset node 121.
Buffer transistor 113 shares with reset transistor 112 second N+ region 118 as a drain. The source of buffer transistor 113 is formed by third heavily doped N type region 122. Photodiode node 123 connects photodiode 111 with gate 124 of buffer transistor 113.
Row select transistor 114 has a source formed by fourth heavily doped N type region 125, which is connected to output node 126. Row select transistor 114 shares with buffer transistor 113 third N+ region 122 as a drain. Gate 127 of row select transistor 114 is connected to row select node 128. The gates, drains and sources of the MOS transistors making up pixel cell 110 all bear silicided surfaces 129.
Pixel cell 110 operates in three steps: a reset step, where the pixel cell is reset from the previous integration cycle; an image integration step, where light energy is collected by the photodiode and converted into an electrical signal; and a signal readout step, where the electrical signal is read out from the photodiode.
TABLE 1 shows a timing diagram illustrating reset, image integration, and readout steps with respect to conventional pixel cell 110.
TABLE 1 ______________________________________ Timing Diagram For Conventional Pixel Cell diode reset row select output time step node node node node ______________________________________ t.sub.1 reset V.sub.fin high low low t.sub.2 int. V.sub.init low high V.sub.init t.sub.3 read V.sub.fin low high V.sub.fin ______________________________________
With reference to FIGS. 1A-1B, the reset step begins by pulsing reset node 121 with a reset voltage at time t.sub.1. The reset voltage turns on reset transistor 112, which pulls up the voltage on photodiode 111 and gate 124 of buffer transistor 113 to an initial integration voltage V.sub.init. The voltage on the source of buffer transistor 113 is in turn pulled up to one threshold voltage drop below V.sub.init, due to the source-follower operation of buffer transistor 113.
After this, the value of the initial integration voltage V.sub.init (less the threshold voltage drop of buffer transistor 113) of photodiode 111 is read out from the pixel cell circuit by pulsing gate 127 of row-select transistor 114 with a row select voltage at time t.sub.2. The row select voltage turns on row select transistor 114, causing V.sub.init on the source of buffer transistor 113 to appear on the source of row select transistor 114, and on output node 126. V.sub.init may then be detected by conventional circuitry, and is stored as a reset value.
Next, during integration, light energy in the form of photons 130 strikes silicided surface 117 of photodiode 111, thereby creating a number of electron-hole pairs. Photodiode 111 is designed to limit recombination between these newly formed electron-hole pairs. As a result, the photogenerated holes are attracted to the ground terminal (not shown) of photodiode 111, while photogenerated electrons are attracted to the positive terminal of photodiode 111 where each additional electron reduces the voltage on photodiode 111.
Following image integration, the final integration voltage V.sub.fin is read out at time t.sub.3. At this time, the final integration voltage V.sub.fin on photodiode 111 (less the threshold voltage of buffer transistor 113), is present on the source of row select transistor 114 due to the source-follower operation of buffer transistor 113. As a result, when a row select voltage is applied to row select node 128 at t.sub.3 turning on row-select transistor 114, the final voltage V.sub.fin on the source of buffer transistor 113 appears on the source of row-select transistor 114 and output node 126. V.sub.fin is detected and then stored as a read value.
Thus, at the conclusion of the integration period, the number of photons absorbed by photodiode 111 during the image integration period can be determined from the difference between V.sub.fin (taken at the end of the integration period) and V.sub.init (taken at the beginning of the integration period). This voltage difference corresponds to the number of electron hole pairs generated on photodiode 111, and hence the amount of incident light energy.
Silicides, such those present on silicided surfaces 129 of pixel cell 110, are extremely useful for providing low impedance contacts between semiconductor devices. Introduction of silicides into a digital circuit thus considerably enhances speed and performance.
However, because silicides are formed from metals, their presence in an analog circuit can cause significant loss of signal integrity. Pixel cell 110 has a substantial analog character. In order to accurately portray the amount of incident light, V.sub.init and V.sub.fin, generated on photodiode 111 must be communicated to output node 126 with minimal degradation. Thus, the presence of silicide layers 129 in pixel cell 110 can seriously degrade signal integrity, disrupting the operation of the circuit.
Other problems are associated with silicides as well. Silicided surface layer 117 of photodiode 111 absorbs most of the incident light falling on photodiode 111, reducing sensitivity. Moreover, leakage at silicided junctions (for example between silicided photodiode 111 and silicided gate 120 of reset transistor 112) is much higher than leakage with nonsilicided junctions. This leakage will effectively limit the signal to noise ratio of the pixel cell, reducing its usefulness in imagers in consumer applications.
Because of the light sensitivity and leakage problems described above, it is desirable to form a pixel cell structure wherein the photodiode surface remains nonsilicided, and moreover, the photodiode is not directly exposed to a silicided junction.